? semiconductor components industries, llc, 2000 september, 2004 ? rev. xxx 1 publication order number: MTY25N60E/d MTY25N60E preferred device power mosfet 25 amps, 600 volts n?channel to?264 this high voltage mosfet uses an advanced termination scheme to provide enhanced voltage?blocking capability without degrading performance over time. in addition, this advanced power mosfet is designed to withstand high energy in the avalanche and commutation modes. designed for high voltage, high speed switching applications in power supplies, converters and pwm motor controls, these devices are particularly well suited for bridge circuits where diode speed and commutating safe operating areas are critical and offer additional safety margin against unexpected voltage transients. ? robust high voltage termination ? avalanche energy specified ? diode is characterized for use in bridge circuits ? i dss and v ds(on) specified at elevated temperature maximum ratings (t c = 25 c unless otherwise noted) rating symbol value unit drain?source voltage v dss 600 vdc drain?gate voltage (r gs = 1 m w ) v dgr 600 vdc gate?source voltage ? continuous ? non?repetitive (t p 10 ms) v gs v gsm 20 40 vdc vpk drain current ? continuous @ t c = 25 c drain current ? single pulse (t p 10 m s) i d i dm 25 65 adc apk total power dissipation derate above 25 c p d 300 2.38 watts w/ c operating and storage temperature range t j , t stg ?55 to 150 c single pulse drain?to?source avalanche energy ? starting t j = 25 c (v dd = 100 vdc, v gs = 10 vdc, peak i l = 25 apk, l = 10 mh, r g = 25 w ) e as 3000 mj thermal resistance ? junction to case thermal resistance ? junction to ambient r q jc r q ja 0.42 40 c/w maximum lead temperature for soldering purposes, 1/8 from case for 10 seconds t l 260 c 25 amperes 600 volts r ds(on) = 210 m w device package shipping ordering information MTY25N60E to?264 25 units/rail http://onsemi.com preferred devices are recommended choices for future use and best overall value. ll = location code y = year ww = work week marking diagram & pin assignment d g to?264 case 340g style 1 MTY25N60E n?channel s llyww 1 2 3 1 gate 3 source 2 drain
MTY25N60E http://onsemi.com 2 electrical characteristics (t j = 25 c unless otherwise noted) characteristic symbol min typ max unit off characteristics drain?source breakdown voltage (v gs = 0, i d = 250 m a) temperature coefficient (positive) v (br)dss 600 ? ? 714 ? ? vdc mv/ c zero gate voltage drain current (v ds = 600 vdc, v gs = 0 vdc) (v ds = 600 vdc, v gs = 0 vdc, t j = 125 c) i dss ? ? ? ? 10 200 m adc gate?body leakage current (v gs = 20 vdc, v ds = 0) i gss ? ? 100 nadc on characteristics (note 1.) gate threshold voltage (v ds = v gs , i d = 250 m adc) threshold temperature coefficient (negative) v gs(th) 2 ? ? 7 4 ? vdc mv/ c static drain?source on?resistance (v gs = 10 vdc, i d = 12.5 adc) r ds(on) ? ? 0.21 ohm drain?source on?voltage (v gs = 10 vdc) (i d = 25 adc) (i d = 12.5 adc, t j = 125 c) v ds(on) ? ? 5.2 ? 6 7 vdc forward transconductance (v ds = 15 vdc, i d = 12.5 adc) g fs 18 ? ? mhos dynamic characteristics input capacitance (v 25 vd v 0vd c iss ? 7300 10220 pf output capacitance (v ds = 25 vdc, v gs = 0 vdc, f = 1.0 mhz ) c oss ? 700 1100 reverse transfer capacitance f = 1 . 0 mhz) c rss ? 110 250 switching characteristics (note 2.) turn?on delay time t d(on) ? 32 60 ns rise time (v dd = 300 vdc, i d = 25 adc, v gs =10vdc t r ? 90 175 turn?off delay time v gs = 10 vdc, r g = 4.7 w ) t d(off) ? 170 300 fall time r g 4.7 w ) t f ? 110 200 gate charge (s fi 8) q t ? 240 350 nc (see figure 8) (v ds = 480 vdc, i d = 25 adc, q 1 ? 30 ? (v ds 480 vdc , i d 25 adc , v gs = 10 vdc) q 2 ? 110 ? q 3 ? 65 ? source?drain diode characteristics forward on?voltage (i s = 25 adc, v gs = 0 vdc) (i s = 25 adc, v gs = 0 vdc, t j = 125 c) v sd ? ? 0.9 0.8 1.2 ? vdc reverse recovery time (s fi 14) t rr ? 620 ? ns (see figure 14) (i 25 adc v 0 vdc t a ? 310 ? (i s = 25 adc, v gs = 0 vdc, di s /dt = 100 a/ m s) t b ? 310 ? reverse recovery stored charge di s /dt = 100 a/ m s) q rr ? 10.42 ? m c internal package inductance internal drain inductance (measured from the drain lead 0.25 from package to center of die) l d ? 4.5 ? nh internal source inductance (measured from the source lead 0.25 from package to source bond pad) l s ? 7.5 ? nh 1. pulse test: pulse width 300 m s, duty cycle 2%. 2. switching characteristics are independent of operating junction temperature.
MTY25N60E http://onsemi.com 3 typical electrical characteristics r ds(on) , drain-to-source resistance (normalized) r ds(on) , drain-to-source resistance (ohms) r ds(on) , drain-to-source resistance (ohms) 10000 1000 100 10 1 0 200 400 500 600 2.5 2 1.5 1 0.5 0 -50 -25 0 25 50 75 100 125 150 v gs = 10 v i d = 12.5 a 0.26 0.24 0.22 0.2 0.18 i d , drain current (amps) 15 v 0.5 0.4 0.3 0.2 0.1 0 0204050 25 c 30 10 50 0 024 68101214 20 v ds , drain-to-source voltage (volts) figure 1. on?region characteristics i d , drain current (amps) i d , drain current (amps) v gs , gate-to-source voltage (volts) figure 2. transfer characteristics i d , drain current (amps) figure 3. on?resistance versus drain current and temperature figure 4. on?resistance versus drain current and gate voltage t j , junction temperature ( c) figure 5. on?resistance variation with temperature v ds , drain-to-source voltage (volts) figure 6. drain?to?source leakage current versus voltage i dss , leakage (na) t j = 25 c v gs = 10 v v ds 10 v v gs = 10 v t j = 100 c -55 c t j = 25 c v gs = 10 v v gs = 0 v 40 30 20 10 2 2.5 3 3.5 4 4.5 5 5.5 6 0204050 30 10 t j = 125 c 16 18 50 0 40 30 20 10 100 300 6 v 8 v 5 v 4 v 100 c 25 c t j = -55 c 25 c 100 c
MTY25N60E http://onsemi.com 4 power mosfet switching switching behavior is most easily modeled and predicted by recognizing that the power mosfet is charge controlled. the lengths of various switching intervals ( d t) are determined by how fast the fet input capacitance can be charged by current from the generator. the published capacitance data is difficult to use for calculating rise and fall because drain?gate capacitance varies greatly with applied voltage. accordingly, gate charge data is used. in most cases, a satisfactory estimate of average input current (i g(av) ) can be made from a rudimentary analysis of the drive circuit so that t = q/i g(av) during the rise and fall time interval when switching a resistive load, v gs remains virtually constant at a level known as the plateau voltage, v sgp . therefore, rise and fall times may be approximated by the following: t r = q 2 x r g /(v gg ? v gsp ) t f = q 2 x r g /v gsp where v gg = the gate drive voltage, which varies from zero to v gg r g = the gate drive resistance and q 2 and v gsp are read from the gate charge curve. during the turn?on and turn?off delay times, gate current is not constant. the simplest calculation uses appropriate values from the capacitance curves in a standard equation for voltage change in an rc network. the equations are: t d(on) = r g c iss in [v gg /(v gg ? v gsp )] t d(off) = r g c iss in (v gg /v gsp ) the capacitance (c iss ) is read from the capacitance curve at a voltage corresponding to the off?state condition when calculating t d(on) and is read at a voltage corresponding to the on?state when calculating t d(off) . at high switching speeds, parasitic circuit elements complicate the analysis. the inductance of the mosfet source lead, inside the package and in the circuit wiring which is common to both the drain and gate current paths, produces a voltage at the source which reduces the gate drive current. the voltage is determined by ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex. the mosfet output capacitance also complicates the mathematics. and finally, mosfets have finite internal gate resistance which effectively adds to the resistance of the driving source, but the internal resistance is difficult to measure and, consequently, is not specified. the resistive switching time variation versus gate resistance (figure 9) shows how typical switching performance is affected by the parasitic circuit elements. if the parasitics were not present, the slope of the curves would maintain a value of unity regardless of the switching speed. the circuit used to obtain the data is constructed to minimize common inductance in the drain and gate circuit loops and is believed readily achievable with board mounted components. most power electronic loads are inductive; the data in the figure is taken with a resistive load, which approximates an optimally snubbed inductive load. power mosfets may be safely operated into an inductive load; however, snubbing reduces switching losses. 100000 10000 1000 10 10 100 1000 24000 20000 16000 12000 8000 4000 0 10 5 0 5 10 15 20 25 gate-to-source or drain-to-source voltage (volts) c, capacitance (pf) figure 7a. capacitance variation v gs v ds figure 7b. high voltage capacitance variation v ds , drain-to-source voltage (volts) c, capacitance (pf) v gs = 0 v v ds = 0 v t j = 25 c c iss c rss v gs = 0 v t j = 25 c c iss c oss c rss c iss c oss c rss 100
MTY25N60E http://onsemi.com 5 v ds , drain-to-source voltage (volts) v gs , gate-to-source voltage (volts) 25 20 0 0.5 0.55 0.6 0.65 0.7 0.75 0.8 0.85 10000 1000 10 1 10 100 12 10 8 6 4 2 0 0 50 100 150 200 250 q g , total gate charge (nc) q2 600 500 400 300 200 100 0 drain?to?source diode characteristics v sd , source-to-drain voltage (volts) figure 10. diode forward voltage versus current i s , source current (amps) figure 9. resistive switching time variation versus gate resistance r g , gate resistance (ohms) t, time (ns) figure 8. gate charge versus gate?to?source voltage qt t j = 25 c i d = 25 a v dd = 300 v i d = 25 a v gs = 10 v t j = 25 c t d(on) t d(off) v gs t f t r 0.9 100 15 10 5 q1 q3 v ds v gs = 0 v t j = 25 c safe operating area the forward biased safe operating area curves define the maximum simultaneous drain?to?source voltage and drain current that a transistor can handle safely when it is forward biased. curves are based upon maximum peak junction temperature and a case temperature (t c ) of 25 c. peak repetitive pulsed power limits are determined by using the thermal response data in conjunction with the procedures discussed in an569, atransient thermal resistance?general data and its use.o switching between the off?state and the on?state may traverse any load line provided neither rated peak current (i dm ) nor rated voltage (v dss ) is exceeded and the transition time (t r ,t f ) do not exceed 10 m s. in addition the total power averaged over a complete switching cycle must not exceed (t j(max) ? t c )/(r q jc ). a power mosfet designated e?fet can be safely used in switching circuits with unclamped inductive loads. for reliable operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than the rated limit and adjusted for operating conditions differing from those specified. although industry practice is to rate in terms of energy, avalanche energy capability is not a constant. the energy rating decreases non?linearly with an increase of peak current in avalanche and peak junction temperature. although many e?fets can withstand the stress of drain?to?source avalanche at currents up to rated pulsed current (i dm ), the energy rating is specified at rated continuous current (i d ), in accordance with industry custom. the energy rating must be derated for temperature as shown
MTY25N60E http://onsemi.com 6 in the accompanying graph (figure 12). maximum energy at currents below rated continuous i d can safely be assumed to equal the values indicated. safe operating area 1 0.1 0.01 1.0e-05 1.0e-04 1.0e-03 1.0e-02 1.0e-01 1.0e+00 1.0e+01 t, time (s) d = 0.5 0.2 r (t) , effective transient thermal resistance (normalized) 0.1 0.05 0.01 3000 2500 1000 0 25 50 75 100 125 150 100 10 1 0.1 0.1 1 10 100 1000 100 m s 1 ms 10 ms dc t j , starting junction temperature ( c) e as , single pulse drain-to-source figure 12. maximum avalanche energy versus starting junction temperature v ds , drain-to-source voltage (volts) figure 11. maximum rated forward biased safe operating area avalanche energy (mj) i d , drain current (amps) r ds(on) limit thermal limit package limit figure 13. thermal response r q jc (t) = r(t) r q jc d curves apply for power pulse train shown read time at t 1 t j(pk) - t c = p (pk) r q jc (t) p (pk) t 1 t 2 duty cycle, d = t 1 /t 2 v gs = 20 v single pulse t c = 25 c i d = 25 a single pulse 2000 1500 500 10 m s 0.02 figure 14. diode reverse recovery waveform di/dt t rr t a t p i s 0.25 i s time i s t b
MTY25N60E http://onsemi.com 7 package dimensions style 1: pin 1. gate 2. drain 3. source dim a min max min max inches 28.0 29.0 1.102 1.142 millimeters b 19.3 20.3 0.760 0.800 c 4.7 5.3 0.185 0.209 d 0.93 1.48 0.037 0.058 e 1.9 2.1 0.075 0.083 f 2.2 2.4 0.087 0.102 g 5.45 bsc 0.215 bsc h 2.6 3.0 0.102 0.118 j 0.43 0.78 0.017 0.031 k 17.6 18.8 0.693 0.740 l 11.0 11.4 0.433 0.449 n 3.95 4.75 0.156 0.187 p 2.2 2.6 0.087 0.102 q 3.1 3.5 0.122 0.137 r 2.15 2.35 0.085 0.093 u 6.1 6.5 0.240 0.256 w 2.8 3.2 0.110 0.125 notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 0.25 (0.010) m tb m j r h n u l p a k c e f d g w 2 pl 3 pl 0.25 (0.010) m yq s 123 ?b? ?q? ?y? ?t? to?264 case 340g?02 issue h
MTY25N60E http://onsemi.com 8 on semiconductor and are trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to make changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. atypicalo parameters which may be provided in scill c data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including atypicalso must be validated for each customer application by customer's technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body , or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthori zed use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. publication ordering information central/south america: spanish phone : 303?308?7143 (mon?fri 8:00am to 5:00pm mst) email : onlit?spanish@hibbertco.com toll?free from mexico: dial 01?800?288?2872 for access ? then dial 866?297?9322 asia/pacific : ldc for on semiconductor ? asia support phone : 303?675?2121 (tue?fri 9:00am to 1:00pm, hong kong time) toll free from hong kong & singapore: 001?800?4422?3781 email : onlit?asia@hibbertco.com japan : on semiconductor, japan customer focus center 4?32?1 nishi?gotanda, shinagawa?ku, tokyo, japan 141?0031 phone : 81?3?5740?2700 email : r14525@onsemi.com on semiconductor website : http://onsemi.com for additional information, please contact your local sales representative. MTY25N60E/d north america literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303?675?2175 or 800?344?3860 toll free usa/canada fax : 303?675?2176 or 800?344?3867 toll free usa/canada email : onlit@hibbertco.com fax response line: 303?675?2167 or 800?344?3810 toll free usa/canada n. american technical support : 800?282?9855 toll free usa/canada europe: ldc for on semiconductor ? european support german phone : (+1) 303?308?7140 (mon?fri 2:30pm to 7:00pm cet) email : onlit?german@hibbertco.com french phone : (+1) 303?308?7141 (mon?fri 2:00pm to 7:00pm cet) email : onlit?french@hibbertco.com english phone : (+1) 303?308?7142 (mon?fri 12:00pm to 5:00pm gmt) email : onlit@hibbertco.com european toll?free access*: 00?800?4422?3781 *available from germany, france, italy, uk, ireland
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